RISC-V: Difference between revisions
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* GitHub: https://github.com/sifive | * GitHub: https://github.com/sifive | ||
* Company: https://www.sifive.com/ | * Company: https://www.sifive.com/ | ||
* Ad/Explanation of SiFive and RISC-V development possibilities: https://www.youtube.com/watch?v=jNnCok1H3-g | |||
* Presentation by Yunsup Lee on May 8, 2018 at the RISC-V Workshop: https://www.youtube.com/watch?v=oRMOe49jEH4&t=575s | |||
Arduino like board using RISC-V processor: | Arduino like board using RISC-V processor: | ||
| Line 18: | Line 20: | ||
* Project: http://www.lowrisc.org/ | * Project: http://www.lowrisc.org/ | ||
* Buy: not available yet (as of 11/2017) | * Buy: not available yet (as of 11/2017) | ||
DARPA Project Report Analyzing the Disruptive Impact of a [RISC V] Silicon Compiler | |||
*https://youtu.be/xkUXC8Fg1ug | |||
=Layers of Abstraction to be Open Sourced= | =Layers of Abstraction to be Open Sourced= | ||
*Software applications to hardware - [https://www.webopedia.com/quick_ref/OSI_Layers.asp] | *Software applications to hardware - [https://www.webopedia.com/quick_ref/OSI_Layers.asp] | ||
*Layers of abstraction - noting the position of [[Instruction Set Architecture]] - [http://theembeddedguy.com/2016/05/15/layers-of-abstraction/]. There is software and hardware. Instruction Set architecture is not hardware - it determines the hardware - or is implemented in hardware - but the dividing line for hardware should perhaps begin with [[Microarchitecture]] - which are the actual circuit paths on chips. | *Layers of abstraction - noting the position of [[Instruction Set Architecture]] - [http://theembeddedguy.com/2016/05/15/layers-of-abstraction/]. There is software and hardware. Instruction Set architecture is not hardware - it determines the hardware - or is implemented in hardware - but the dividing line for hardware should perhaps begin with [[Microarchitecture]] - which are the actual circuit paths on chips. | ||
=See Also= | |||
*[[SiFive]] | |||
Latest revision as of 01:26, 14 January 2019
Intro
https://fosdem.org/2018/schedule/event/riscv/
More
Open Source (BSD license) CPU. The RISC-V CPU going to production is a game changer for the Open Source Hardware community. Note that the hardware used is not open source. The part that is open source is the Instruction Set Architecture. The next revolution towards true open source comes when the actual semiconductor fabrication will become open source, which currently does not exist, and is one of the last frontiers for OSE and the open hardware non-movement.
- Wikipedia: https://en.wikipedia.org/wiki/RISC-V
- GitHub: https://github.com/sifive
- Company: https://www.sifive.com/
- Ad/Explanation of SiFive and RISC-V development possibilities: https://www.youtube.com/watch?v=jNnCok1H3-g
- Presentation by Yunsup Lee on May 8, 2018 at the RISC-V Workshop: https://www.youtube.com/watch?v=oRMOe49jEH4&t=575s
Arduino like board using RISC-V processor:
Raspberry Pi like board using RISC-V processor:
- Project: http://www.lowrisc.org/
- Buy: not available yet (as of 11/2017)
DARPA Project Report Analyzing the Disruptive Impact of a [RISC V] Silicon Compiler
Layers of Abstraction to be Open Sourced
- Software applications to hardware - [1]
- Layers of abstraction - noting the position of Instruction Set Architecture - [2]. There is software and hardware. Instruction Set architecture is not hardware - it determines the hardware - or is implemented in hardware - but the dividing line for hardware should perhaps begin with Microarchitecture - which are the actual circuit paths on chips.